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FEDL63187B-06
1 Semiconductor ML63187B/63189B
GENERAL DESCRIPTION
This version: Sep. 2001 Previous version: Mar. 2000
4-Bit Microcontroller with Built-in1024-Dot Matrix LCD Drivers and Melody Circuit, Operating at 0.9 V (Min.)
The ML63187B and ML63189B are CMOS 4-bit microcontroller with built-in 1024-dot matrix LCD drivers and operates at 0.9 V (min.). The ML63187B and 63189B are suitable for applications such as games, toys, watches, etc. which are provided with an LCD display. The ML63187B and ML63189B are M6318x series mask ROM-version product of OLMS-63K family, which employs Oki's original CPU core nX-4/250.
FEATURES
* Rich instruction set 408 instructions Transfer, rotate, increment/decrement, arithmetic operations, comparison, logic operations, mask operations, bit operations, ROM table reference, stack operations, flag operations, branch, conditional branch, call/return, control * Rich selection of addressing modes Indirect addressing of four data memory types, with current bank register, extra bank register, HL register and XY register Data memory bank internal direct addressing mode * Processing speed Two clocks per machine cycle, with most instructions executed in one machine cycle Minimum instruction execution time : 61 s (@32.768 kHz system clock) 1 s (@2 MHz system clock) * Clock generation circuit Low-speed clock : Crystal oscillation or RC oscillation selected with mask option (30 to 80 kHz) High-speed clock : Ceramic oscillation or RC oscillation selected with software (2 MHz max.) * Program memory space * ML63187B : 16 K words * ML63189B : 32 K words Basic instruction length is 16 bits/1 word * Data memory space * ML63187B : 1024 nibbles * ML63189B : 1536 nibbles * Stack level Call stack level Register stack level
: 16 levels : 16 levels
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
* I/O ports Input ports:
Selectable as input with pull-up resistor/input with pull-down resistor/high-impedance input Input-output ports: Selectable as input with pull-up resistor/input with pull-down resistor/high-impedance input Selectable as P-channel open drain output/N-channel open drain output/CMOS output/high-impedance output Can be interfaced with external peripherals that use a different power supply than this device uses. VDD is the power supply pin for ports. Number of ports: ML63187B Input-output port : 2 ports x 4 bits ML63189B Input port : 1 port x 4 bits Input-output port : 4 ports x 4 bits
* Melody output Melody frequency Tone length Tempo Melody data Buzzer driver signal output * LCD driver Number of segments Duty Bias Frame frequency Contrast Display modes
: : : : :
529 to 2979 Hz 63 types 15 types Resides in the program memory 4 kHz
: 1024 Max. (64 SEG x 16 COM) : 1/1 to 1/16 duty : Selectable as 1/4 or 1/5 bias regulator circuit built-in : 64 Hz (at 1/16 duty) , 128 Hz (at 1/8 duty ) , 256 Hz (at 1/4 duty) , 512Hz (at 1/2 duty) , 1024 Hz (at 1/1 duty ) : A maximum of 16 levels adjustable : Selectable s all-ON mode/all-OFF mode/power down mode/normal display mode adjustable contrast.
* System reset function * System reset by RESET pin (Built-in 2 kHz RESET sampling circuit can be selected by mask option) * System reset by power-on detection (When not using 2 kHz RESET sampling circuit) * System reset by detection that low-speed clock has stopped oscillation * Battery check Low-voltage supply check The value of the judgment voltage is selected by the software by setting the LD1 and LD0 bits of BLDCON.
LD1 0 0 1 1 LD0 0 1 0 1 Judgment Voltage (V) 1.05 0.10 1.20 0.10 1.80 0.10 2.40 0.10 Remarks Ta = 25C Ta = 25C Ta = 25C Ta = 25C
* Power supply backup Backup circuit (voltage multiplier) enables operation at 0.9 V minimum
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Semiconductor 1
ML63187B/63189B
* Timers and counter 8-bit timer x 4 Selectable as auto-reload mode/capture mode/clock frequency measurement mode Watchdog timer x 1 100 Hz timer x 1 Measurable in steps of 1/100 sec. 15-bit time base counter x 1 1, 2, 4, 8, 16, 32, 64, and 128 Hz signals can be read * Shift register Shift clock Data length * Interrupt sources ML63187B External interrupt Internal interrupt ML63189B External interrupt Internal interrupt * Operating temperature -20 to +70C * Operating voltage When backup used : 1 x or 1/2 x system clock, timer 1 overflow, external clock : 8 bits
:2 : 12 (watchdog timer interrupt is a nonmaskable interrupt) :3 : 12 (watchdog timer interrupt is a nonmaskable interrupt)
When backup not used
: 0.9 to 2.7 V (Operating frequency: 30 to 80 kHz) 1.2 to 2.7 V (Operating frequency: 300 to 500 kHz) 1.5 to 2.7 V (Operating frequency: 200 kHz to 1 MHz) : 1.8 to 5.5 V (Operating frequency: 200 kHz to 2 MHz)
* Package: Chip (ML63187B: 111 pads , ML63189B: 123 pads): (Product name: ML63187B-xxxWA, ML63189B-XXXWA) 128-pin plastic QFP (QFP128-P-1420-0.50-K) : (Product name: ML63187B-xxxGA, ML63189B-xxxGA) xxx indicates a code number.
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
MASK OPTION
In the ML63187B and ML63189B use the mask option to specify the following functions: * Low-Speeed clock oscillation circuit Specify the crystal oscillation circuit or the RC oscillation circuit for the low-speed clock oscillation circuit. * Reset signal sampling Specify whether or not the reset signal will be sampled at 2 kHz. When specifying "will carry out 2 kHz sampling," hold the RESET pin at a "H" level for 1 ms or more. To use the mask option, assign mask option data in the application program in accordance with the formats below. The mask option area for each device is an application program execution disabled area. Mask Option Data Assignment Format
Function Low-speed clock oscillation circuit (crystal oscillation circuit/RC oscillation circuit) Reset signal sampling (will/will not carry out 2 kHz sampling) Mask option area bit data 0 1 0 1 Option to be selected Crystal oscillation circuit RC oscillation circuit Will carry out 2 kHz sampling Will not carry out 2 kHz sampling
ML63187B:3FE0H bit 0 ML63189B:7FE0H bit 1
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Semiconductor 1
ML63187B/63189B
BLOCK DIAGRAM (ML63187B)
An asterisk (*) indicates the port secondary function. indicates that the power is supplied to the circuits corresponding to the signal names inside from VDDI (power supply for interface).
CPU CORE
CBR H
nX-4/250
L RA PC
TIMING CONTROL
ROM 16 KW
EBR SP RSP
X
Y C
A G MIE Z BUS CONTROL
ALU
STACK CAL : 16-level REG : 16-level
INSTRUCTION DECODER
IR
INT 4 RAM 1024N TIMER 8 bit x 4 TM0CAP/TM1CAP* TM0OVF/TM1OVF* T02CK* T13CK*
RESET
RST INT
INT187 INT 1 TBC SFT DATA BUS SCLK* SIN* SOUT* BLD
TST1 TST2
TST
4
XT0 XT1 OSC0 OSC1 INT 1 OSC INT 1
100 HzTC
INT 1 MELODY
MD MDB
WDT
VDDH VDD CB1 CB2 VDD1 VDD2 VDD3 VDD4 VDD5 C1 C2 VDDL VDD1 VSS
BIAS LCD & DSPR COM1-16 SEG0-63 BACK UP INT 2 I/O PORT PB.0-PB.3 PE.0-PE.3
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
BLOCK DIAGRAM (ML63189B)
An asterisk (*) indicates the port secondary function. indicates that the power is supplied to the circuits corresponding to the signal names inside from VDDI (power supply for interface).
CPU CORE
CBR H
nX-4/250
L RA PC
TIMING CONTROL
ROM 32 KW
EBR SP RSP
X
Y C
A G MIE Z BUS CONTROL
ALU
STACK CAL : 16-level REG : 16-level
INSTRUCTION DECODER
IR
INT 4 RAM 1536N TIMER 8 bit x 4 TM0CAP/TM1CAP* TM0OVF/TM1OVF* T02CK* T13CK*
INT RESET RST INT 4 TST1 TST2 TST TBC DATA BUS INT 1 MELODY INT189 1 SFT SCLK* SIN* SOUT*
MD MDB
BLD XT0 XT1 OSC OSC0 OSC1 INT 1 INT 1 WDT 100 HzTC
INT 1 INPUT PORT P0.0-P0.3
VDDH VDD CB1 CB2 VDD1 VDD2 VDD3 VDD4 VDD5 C1 C2 VDDL
BIAS LCD & DSPR INT 2 BACK UP I/O PORT
P9.0-P9.3 PA.0-PA.3 PB.0-PB.3 PE.0-PE.3
COM1-16 SEG0-63
VDDI VSS
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
PIN CONFIGURATION (TOP VIEW) (ML63187B)
(NC) (NC) (NC) (NC) SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM9 COM10 COM11 COM12 (NC) (NC) (NC) (NC)
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
(NC) (NC) (NC) (NC) SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 PB.3 PB.2 PB.1 PB.0 PE.3 PE.2 PE.1 PE.0 VDDI (NC) (NC) (NC) (NC) (NC)
Note:
COM13 COM14 COM15 COM16 VSS VDD1 V DD2 V DD3 V DD4 V DD5 C1 C2 V DDH CB1 CB2 V DD V DDL OSC1 OSC0 RESET XT1 XT0 TST1 TST2 MD MDB
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
128-Pin Plastic QFP Pins marked as (NC) are no-connection pins which are left open.
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Semiconductor 1
ML63187B/63189B
PAD CONFIGURATION (ML63187B)
Pad Layout
MDB MD TST2 TST1 XT0 XT1 RESET OSC0 OSC1 VDDL VDD CB2 CB1 VDDH C2 C1 VDD5 VDD4 VDD3 VDD2 VDD1 VSS COM16 COM15 COM14 COM13 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
VDDI PE.0 PE.1 PE.2 PE.3 PB.0 PB.1 PB.2 PB.3 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11
83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111
Y
(0,0)
X
COM12 COM11 COM10 COM9 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38
SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 Chip size Chip thickness Coordinate origin Pad hole size Pad size Minimum pad pitch : 4.238 mm x 4.914 mm : 350 m (280 m: available as required) : center of chip : 100 m x 100 m : 110 m x 110 m : 140 m
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Note: The chip substrate voltage is VSS.
ML63187
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Semiconductor 1
ML63187B/63189B
Pad Coordinates (ML63187B)
Center of chip: X = 0, Y = 0 Pad No. Pad Name X (m) Y (m) Pad No. Pad Name X (m) Y (m) Pad No. Pad Name X (m) Y (m) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 -1755 -2311 -1615 -2311 -1474 -2311 -1334 -2311 -1193 -2311 -1053 -2311 -913 -2311 -772 -2311 -632 -2311 491 -2311 -351 -2311 -211 -2311 -70 -2311 70 -2311 211 -2311 351 -2311 491 -2311 632 -2311 772 -2311 913 -2311 1053 -2311 1193 -2311 1334 -2311 1474 -2311 1615 -2311 1755 -2311 1969 -2036 1969 -1895 1969 -1755 1969 -1615 1969 -1474 1969 -1334 1969 -1193 1969 -1053 1969 1969 1969 1969 1969 1969 1969 -913 -772 -632 491 -351 -211 -70 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 VSS VDD1 VDD2 VDD3 VDD4 VDD5 C1 C2 VDDH CB1 CB2 VDD VDDL OSC1 OSC0 RESET XT1 XT0 TST1 TST2 MD MDB 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1969 1755 1615 1474 1334 1193 1053 913 772 632 491 351 211 70 -70 -211 -351 -491 -632 -772 -913 -1053 -1193 -1334 -1474 -1615 -1755 70 211 351 491 632 772 913 1053 1193 1334 l 474 1615 1755 1895 2036 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 2311 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 VDDI PE.0 PE.1 PE.2 PE.3 PB.0 PB.1 PB.2 PB.3 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 -1969 1895 1755 1615 1474 1334 1193 1053 913 772 632 491 351 211 70 -70 -211 -351 -491 -632 -772 -913
-1969 -1053 -1969 -1193 -1969 -1334 -1969 -1474 -1969 -1615 -1969 -1755 -1969 -1895 -1969 -2036
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Semiconductor 1
ML63187B/63189B
PIN CONFIGURATION (TOP VIEW) (ML63189B)
SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 (NC) SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM9 COM10 (NC) SEG7 SEG6 SEG5 SEG4
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
(NC) SEG3 SEG2 SEG1 SEG0 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 P0.3 P0.2 P0.1 P0.0 P9.3 P9.2 P9.1 P9.0 PA.3 PA.2 PA.1 PA.0 PB.3 PB.2 PB.1 PB.0 PE.3 PE.2 PE.1 PE.0 VDDI (NC) MDB MD (NC)
Note:
COM11 COM12 COM13 COM14 COM15 COM16 VSS VDD1 VDD2 VDD3 VDD4 VDD5 C1 C2 VDDH CB1 CB2 VDD VDDL OSC1 OSC0 RESET XT1 XT0 TST1 TST2
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
128-Pin Plastic QFP Pins marked as (NC) are no-connection pins which are left open.
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
PAD CONFIGURATION (ML63189B)
Pad Layout
MD TST2 TST1 XT0 XT1 RESET OSC0 OSC1 VDDL VDD CB2 CB1 VDDH C2 C1 VDD5 VDD4 VDD3 VDD2 VDD1 VSS COM16 COM15 COM14 COM13 COM12 COM11 COM10 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 COM9 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
92
MDB
VDDI PE.0 PE.1 PE.2 PE.3 PB.0 PB.1 PB.2 PB.3 PA.0 PA.1 PA.2 PA.3 P9.0 P9.1 P9.2 P9.3 P0.0 P0.1 P0.2 P0.3 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 SEG0 SEG1
93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
ML63189B
Y
(0,0)
X
SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 Chip size Chip thickness Coordinate origin Pad hole size Pad size Minimum pad pitch : 4.81 mm x 5.20 mm : center of chip : 100 m x 100 m : 110 m x 110 m : 140 m
: 350 m (280 m: available as required)
Note: The chip substrate voltage is VSS.
SEG31
SEG2
30
1
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
Pad Coordinates (ML63189B)
Center of chip: X = 0, Y = 0 Pad No. Pad Name X (m) Y (m) Pad No. Pad Name X (m) Y (m) Pad No. Pad Name X (m) Y (m) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 -2259 -2438 -1895 -2438 -1755 -2438 -1615 -2438 -1474 -2438 -1334 -2438 -1193 -2438 -1053 -2438 -913 -2438 -772 -2438 -632 -2438 -491 -2438 -351 -2438 -211 -2438 -70 -2438 70 -2438 211 -2438 351 -2438 491 -2438 632 -2438 772 -2438 913 -2438 1053 -2438 1193 -2438 1334 -2438 1474 -2438 1615 -2438 1755 -2438 1895 -2438 2259 -2438 2259 -2176 2259 -2036 2259 -1895 2259 -1755 2259 -1615 2259 -1474 2259 -1334 2259 -1193 2259 -1053 2259 2259 -913 -772 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 VSS VDD1 VDD2 VDD3 VDD4 VDD5 C1 C2 VDDH CB1 CB2 VDD 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 2259 1895 1755 1615 1474 1334 1193 1053 913 772 632 491 351 211 70 -70 -211 -351 -491 -632 -632 -491 -351 -211 -70 70 211 351 491 632 772 913 1053 1193 1334 1474 1615 1755 1895 2036 2176 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 VDDL OSC1 OSC0 RESET XT1 XT0 TST1 TST2 MD MDB VDDI PE.0 PE.1 PE.2 PE.3 PB.0 PB.1 PB.2 PB.3 PA.0 PA.1 PA.2 PA.3 P9.0 P9.1 P9.2 P9.3 P0.0 P0.1 P0.2 P0.3 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 SEG0 SEG1 -772 -913 -1053 -1193 -1334 -1474 -1615 -1755 -1895 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 -2259 2438 2438 2438 2438 2438 2438 2438 2438 2438 2438 2132 1895 1755 1615 1474 1334 1193 1053 913 772 632 491 351 211 70 -70 -211 -351 -491 -632 -772 -913
-2259 -1053 -2259 -1193 -2259 -1334 -2259 -1474 -2259 -1615 -2259 -1755 -2259 -1895 -2259 -2036 -2259 -2176
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Semiconductor 1
ML63187B/63189B
PIN DESCRIPTIONS
The basic functions of each pin of the ML63187B, ML63189B are described in Table 1. A symbol with a slash (/) denotes a pin that has a secondary function. Refer to Table 2 for secondary functions. For type, "--" denotes a power supply pin, "I" an input pin, "O" an output pin, and "I/O" an input-output pin. Table 1 Pin Descriptions (Basic Functions)
Function Symbol VDD VSS VDD1 VDD2 VDD3 VDD4 VDD5 C1 C2 Power Supply VDDI Pin No. 54 43 44 45 46 47 48 49 50 70 56 45 46 47 48 49 50 51 52 69 Pad No. 72 61 62 63 64 65 66 67 68 83 82 71 72 73 74 75 76 77 78 93 -- -- -- Capacitor connection pins for LCD bias generation A capacitor (0.1 F) should be connected between C1 and C2. Positive power supply pin for external interface (power supply for input, and input-output ports) Positive power supply pin for internal logic (internally generated) A capacitor (0.1 F) should be connected between this pin and VSS. Voltage multiplier pin for power supply backup (internally generated) A capacitor (1.0 F) should be connected between this pin and VSS. Pins to connect a capacitor for voltage multiplier A capacitor (1.0 F) should be connected between CB1 and CB2. Low-speed clock oscillation pins An option for using crystal oscillation or RC oscillation is chosen by the mask option. If the crystal oscillation is chosen, a crystal should be connected between XT0 and XT1, and capacitor (CG) should be connected between XT0 and VSS. If the RC oscillation is chosen, external oscillation resistor (ROSL) should be connected between XT0 and XT1. High-speed clock oscillation pins A ceramic resonator and capacitors (CL0, CL1 ) or external oscillation resistor (ROSH) should be connected to these pins. -- Type -- -- Description Positive power supply Negative power supply Power supply pins for LCD bias (internally generated) Capacitors (0.1 F) should be connected between these pins and VSS.
ML63187B ML63189B ML63187B ML63189B
VDDL
55
57
73
83
--
VDDH
51
53
69
79
--
CB1 CB2
52 53
54 55
70 71
80 81
-- --
XT0
60
62
78
88
I
Oscillation
XT1
59
61
77
87
O
OSC0 OSC1
57 56
59 58
75 74
85 84
I O
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
Table 1 Pin Descriptions (Basic Functions) (continued)
Function Symbol TST1 Test TST2 62 64 80 90 I Pin No. Pad No. Type I Description Input pins for testing A pull-down resistor is internally connected to these pins. The user cannot use these pins. Reset input pin Setting this pin to "H" Ievel puts this device into a reset state. Then, setting this pin to "L" Ievel starts executing an instruction from address 0000H. A pull-down resistor is internally connected to this pin. An option of using RESET sampling circuit or not is chosen by the mask option. When using RESET sampling circuit, the system reset mode is entered by holding the RESET pin at a "H" Ievel for 1 ms or more. Melody output pin (non-inverted output) Melody output pin (inverted output) 4-bit input ports Pull-up resistor input, pull-down resistor input, or high-impedance input is selectable for each bit. Applied to the ML63189B only. 4-bit input-output ports In input mode, pull-up resistor input, pulldown resistor input, or high-impedance input is selectable for each bit. In output mode, P-channel open drain output, N-channel open drain output, CMOS output, or high-impedance output is selectable for each bit. P9.0 to P9.3 and PA.0 to PA.3 are applied to the ML63189B only.
ML63187B ML63189B ML63187B ML63189B
61
63
79
89
Reset
RESET
58
60
76
86
I
Melody
MD MDB P0.0/INT5 P0.1/INT5 P0.2/INT5 P0.3/INT5 P9.0 P9.1 P9.2 P9.3 PA.0 PA.1 PA.2 PA.3
63 64
66 67 86 87 88 89 82 83 84 85 78 79 80 81
81 82
91 92 110 111 112 113 106 107 108 109 102 103 104 105
O O
--
--
I
--
--
I/O
--
--
I/O
Port
PB.0/INT0/ TM0CAP/ TM0OVF PB.1/INT0/ TM1CAP/ TM1OVF PB.2/INT0/ T02CK PB.3/INT0/ T13CK PE.0/SIN PE.1/SOUT PE.2/SCLK PE.3/INT2
75
74
88
98
76 77 78 71 72 73 74
75 76 77 70 71 72 73
89 90 91 84 85 86 87
99 100 101 94 95 96 97
I/O
I/O
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
Table 1 Pin Descriptions (Basic Functions) (continued)
Function Symbol COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 SEG0 SEG1 SEG2 SEG3 SEG4 LCD SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 Pin No. 79 80 81 82 83 84 85 86 31 32 33 34 39 40 41 42 87 88 89 90 91 92 93 94 95 96 97 98 103 104 105 106 107 108 109 110 111 112 113 114 115 90 91 92 93 94 95 96 97 36 37 39 40 41 42 43 44 98 99 100 101 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 Pad No. 92 93 94 95 96 97 98 99 53 54 55 56 57 58 59 60 100 101 102 103 104 105 106 107 108 109 110 111 1 2 3 4 5 6 7 8 9 10 11 12 13 114 115 116 117 118 119 120 121 63 64 65 66 67 68 69 70 122 123 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 O LCD segment signal output pins Type Description LCD common signal output pins
ML63187B ML63189B ML63187B ML63189B
O
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
Table 1 Pin Descriptions (Basic Functions) (continued)
Function Symbol SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 LCD SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 Pin No. 116 117 118 119 120 121 122 123 124 125 126 127 128 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 124 125 126 127 128 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Pad No. 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 O Type Description LCD segment signal output pins
ML63187B ML63189B ML63187B ML63189B
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
Table 2 shows the secondary functions of each pin of the ML63187B, ML63189B. Table 2 Pin Descriptions (Secondary Functions)
Function Symbol PB.0/INT0 PB.1/INT0 PB.2/INT0 PB.3/INT0 External Interrupt PE.3/INT2 P0.0/INT5 P0.1/INT5 -- P0.2/INT5 P0.3/INT5 PB.0/TM0CAP Capture PB.1/TM1CAP PB.0/TM0OVF PB.1/TM1OVF Timer PB.2/T02CK PB.3/T13CK PE.0/SIN Shift Register PE.1/SOUT PE.2/SCLK 77 78 71 72 73 76 77 70 71 72 90 91 84 85 86 100 101 94 95 96 I I I O I/O 76 75 76 75 74 75 89 88 89 99 98 99 I O O Timer 1 capture input pin Timer 0 overflow flag output pin Timer 1 overflow flag output pin External clock input pin for timer 0 and timer 2 External clock input pin for timer 1 and timer 3 Shift register receive data input pin Shift register transmit data output pin Shift register clock input-output pin Clock output when this device is used as a master processor. 75 88 89 74 88 Pin No. 75 76 77 78 74 74 75 76 77 73 86 87 -- 112 113 98 I Pad No. 88 89 90 91 87 98 99 I 100 101 97 110 111 I I Type Description External 0 interrupt input pins The change of input signal level causes an interrupt to occur. The Port B Interrupt Enable register (PBIE) enables or disables an interrupt for each bit. External 2 interrupt input pin The change of input signal level causes an interrupt to occur. External 5 interrupt input pins The change of input signal level causes an interrupt to occur. The Port 0 Interrupt Enable register (P0IE) enable or disable an interrupt for each bit. Applied to the ML63189B only. Timer 0 capture input pin
ML63187B ML63189B ML63187B ML63189B
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
ABSOLUTE MAXIMUM RATINGS
(VSS = 0 V) Parameter Power Supply Voltage 1 Power Supply Voltage 2 Power Supply Voltage 3 Power Supply Voltage 4 Power Supply Voltage 5 Power Supply Voltage 6 Power Supply Voltage 7 Power Supply Voltage 8 Power Supply Voltage 9 Input Voltage 1 Input Voltage 2 Output Voltage 1 Output Voltage 2 Output Voltage 3 Output Voltage 4 Output Voltage 5 Output Voltage 6 Output Voltage 7 Output Voltage 8 Storage Temperature Symbol VDD1 VDD2 VDD3 VDD4 VDD5 VDD VDDI VDDH VDDL VIN1 VIN2 VOUT1 VOUT2 VOUT3 VOUT4 VOUT5 VOUT6 VOUT7 VOUT8 TSTG Condition Ta = 25C Ta = 25C Ta = 25C Ta = 25C Ta = 25C Ta = 25C Ta = 25C Ta = 25C Ta = 25C VDD Input, Ta = 25C VDDI Input, Ta = 25C VDD1 Output, Ta = 25C VDD2 Output, Ta = 25C VDD3 Output, Ta = 25C VDD4 Output, Ta = 25C VDD5 Output, Ta = 25C VDD Output, Ta = 25C VDDI Output, Ta = 25C VDDH Output, Ta = 25C -- Rating -0.3 to +1.6 -0.3 to +2.9 -0.3 to +4.2 -0.3 to +5.5 -0.3 to +6.8 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0 -0.3 to VDD +0.3 -0.3 to VDDI +0.3 -0.3 to VDD1 +0.3 -0.3 to VDD2 +0.3 -0.3 to VDD3 +0.3 -0.3 to VDD4 +0.3 -0.3 to VDD5 +0.3 -0.3 to VDD +0.3 -0.3 to VDDI +0.3 -0.3 to VDDH +0.3 -55 to +150 Unit V V V V V V V V V V V V V V V V V V V C
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
RECOMMENDED OPERATING CONDITIONS
* When backup is used
(VSS = 0 V) Parameter Operating Temperature Operating Voltage Crystal Oscillation Frequency Low-Speed RC Oscillation Frequency Symbol Top VDD VDDI fXT fROSL Condition -- -- -- CG = 5 to 25 pF ROSL = 1.0 M ROSL = 1.1 M ROSL = 1.2 M VDD = 0.9 to 1.2 V Ceramic Oscillation Frequency fCM VDD = 1.2 to 2.7 V VDD = 1.5 to 2.7 V VDD = 0.9 to 1.2 V High-speed RC Oscillation Frequency fROSH ROSH = 400 k VDD = 1.2 to 2.7 V ROSH = 100 k ROSH = 75 k Range -20 to +70 0.9 to 2.7 0.9 to 5.5 32.768 to 76.8 36 30% 33 30% 30 30% Not applied 300k to 500k 200k to 1M Not applied 200k 30% 700k 30% 1M 30% Hz Hz kHz Unit C V V kHz
* When backup is not used
(VSS = 0 V) Parameter Operating Temperature Operating Voltage Crystal Oscillation Frequency Low-Speed RC Oscillation Frequency Ceramic Oscillation Frequency High-speed RC Oscillation Frequency Symbol Top VDD VDDI fXT fROSL fCM Condition -- -- -- CG = 5 to 25 pF ROSL = 1.0 M ROSL = 1.1 M ROSL = 1.2 M VDD = 1.8 to 5.5 V ROSH = 100 k fROSH VDD = 1.8 to 5.5 V ROSH = 75 k ROSH = 51 k VDD = 1.8 to 3.5 V, ROSH = 30 k Range -20 to +70 1.8 to 5.5 1.8 to 5.5 32.768 to 76.8 36 30% 33 30% 30 30% 200k to 2M 700k 30% 1M 30% 1.35M 30% 2M 30% Hz Hz kHz Unit C V kHz
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
* Typical characteristics of low-speed RC oscillation When backup is used/backup is not used (VDD = VDDI = 1.5 V/VDD = VDDI = 3.0 V)
Reference data 1000 fROSL [kHz] 100 10 100
1000
ROSL [k]
10000
* Typical characteristics of high-speed RC oscillation When backup is used (VDD = VDDI = 1.5 V)
Reference data 10000 fROSH [kHz] 1000 100 10
100 ROSH [k]
1000
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
* Typical characteristics of high-speed RC oscillation When backup is not used (VDD = VDDI = 3.0 V)
Reference data 10000 fROSH [kHz] 1000 100 10
100 ROSH [k]
1000
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
(VDD = VDDI = 0.9 to 5.5 V, VSS = 0 V, Ta = -20 to +70C unless otherwise specified)
Parameter VDD2 Voltage VDD2 Voltage Temperature Deviation VDD1 Voltage VDD3 Voltage VDD4 Voltage VDD5 Voltage Symbol VDD2 VDD2 VDD1 VDD3 VDD4 VDD5 Condition 1/5 bias, 1/4 bias (Ta = 25C) -- 1/5 bias, 1/4 bias 1/5 bias 1/4 bias (connect VDD3 and VDD2) 1/5 bias 1/4 bias 1/5 bias 1/4 bias High-speed clock oscillation stopped VDDH Voltage (Backup used) VDDH
VDD = 1.5 V
Min. 1.7 --
Typ. - 0.1 Typ. - 0.3 Typ. - 0.2 Typ. - 0.4 Typ. - 0.3 Typ. - 0.5 Typ. - 0.4
Typ. 1.8 -4
1/2 x VDD2 3/2 x VDD2
Max. 1.9 --
Typ. + 0.1 Typ. + 0.3 Typ. + 0.2 Typ. + 0.4 Typ. + 0.3 Typ. + 0.5 Typ. + 0.4
Unit V
mV/C
Measuring Circuit
V V V V
VDD2
2 x VDD2 3/2 x VDD2 5/2 x VDD2 2 x VDD2
2.8
--
3.0
V
High-speed clock oscillation (Ceramic oscillation, 1 MHz) VDD = 1.5 V High-speed clock oscillation stopped High-speed clock oscillation (VDD = 1.2 to 5.5 V) Oscillation start time: within 5 seconds Backup Backup not used -- -- -- CSA2.00MG (Murata MFG.-make) used VDD = 3.0 V -- VDD = 1.5 V VDD = 3.0 V VDD = 1.5 V VDD = 3.0 V LD1 = 1, LD0 = 1, Ta = 25C LD1 = 1, LD0 = 0, Ta = 25C LD1 = 0, LD0 = 1, Ta = 25C LD1 = 0, LD0 = 0, Ta = 25C VBLDC = 2.40 V (LD1 = 1, LD0 = 1)
2.0
--
2.7
V
1.0 1.2 1.2 0.9 1.7 0.1 5 20
1.5 -- -- -- -- -- -- 25
2.0 5.5 -- -- -- 5.0 25 30
V V V V V ms pF pF
VDDL Voltage
VDDL
1
Crystal Oscillation Start Voltage Crystal Oscillation Hold Voltage Crystal Oscillation Stop Detect Time External Crystal Oscillator Capacitance Internal Crystal Oscillator Capacitance External Ceramic Oscillator Capacitance Internal RC Oscillator Capacitance POR Voltage Non-POR Voltage
VSTA VHOLD TSTOP CG CD
CL0,1
--
30
--
pF
COS VPOR1 VPOR2
8 0 0 1.2 2.0 2.30 1.70 1.10 0.95 -- -- -- --
12 -- -- -- -- 2.40 1.80 1.20 1.05 -3.5 -2.3 -1.6 -1.2
16 0.4 0.7 1.5 3.0 2.50 1.90 1.30 1.15 -- -- -- --
pF V V V V
BLD Judgment Voltage
VBLDC
V --
mV/C
BLD Judgment Voltage Temperature Deviation
VBLDC
VBLDC = 1.80 V (LD1 = 1, LD0 = 0) VBLDC = 1.20 V (LD1 = 0, LD0 = 1) VBLDC = 1.05 V (LD1 = 0, LD0 = 0)
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
Notes: 1. "TSTOP" indicates that if the crystal oscillator stops over the value of TSTOP, the system reset occurs. 2. "POR" denotes Power On Reset. 3. "VPOR1" indicates that POR occurs when VDD falls from VDD to VPOR1 and again rises up to VDD. 4. "VPOR2" indicates that POR does not occur when VDD falls from VDD to VPOR2 and again rises up to VDD.
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
DC Characteristics (2) * When backup is used
(32.768 kHz crystal is used for the low-speed clock, VDD = VDDI = 1.5 V, VSS = 0 V, 1/5 bias, LCD contrast (DSPCNT) = 0H, Ta = -20 to +70C unless otherwise specified) Parameter Symbol Condition CPU is in HALT state. (High-speed clock oscillation stopped) CPU is in HALT state. LCD is in Power Down mood. (High-speed clock oscillation stopped) CPU is in operation at low-speed oscillation. (High-speed clock oscillation stopped) Ta = -20 to +50C Ta = -20 to +70C Ta = -20 to +50C Min. -- -- -- Typ. 5 5 4 Max. 6.5 10 5 A Ta = -20 to +70C Ta = -20 to +50C Ta = -20 to +70C -- -- -- 4 16 16 8 18 A 20 A A 1 Unit Measuring Circuit
Supply Current 1
IDD1
A
Supply Current 2
IDD2
Supply Current 3
IDD3
Supply Current 4
IDD4
CPU is in operation at high-speed oscillation (approx. 700 kHz RC oscillation, ROSH = 100 k ) CPU is in operation at high-speed oscillation (Ceramic oscillation, 1 MHz)
--
800
1000
Supply Current 5
IDD5
--
700
850
* When backup is not used
(32.768 kHz crystal is used for the low-speed clock, VDD = VDDI = 3.0 V, VSS = 0 V, 1/5 bias, LCD contrast (DSPCNT) = 0H, Ta = -20 to +70C unless otherwise specified) Parameter Symbol Condition CPU is in HALT state. (High-speed clock oscillation stopped) CPU is in HALT state. LCD is in Power Down mood. (High-speed clock oscillation stopped) CPU is in operation at low-speed oscillation. (High-speed clock oscillation stopped) Ta = -20 to +50C Ta = -20 to +70C Ta = -20 to +50C Min. -- -- -- Typ. 2.2 2.2 1.8 Max. 3 5 2.5 A Ta = -20 to +70C Ta = -20 to +50C Ta = -20 to +70C -- -- -- 1.8 7.5 7.5 4 9 A 12 A A 1 Unit Measuring Circuit
Supply Current 1
IDD1
A
Supply Current 2
IDD2
Supply Current 3
IDD3
Supply Current 4
IDD4
CPU is in operation at high-speed oscillation (approx. 700 kHz RC oscillation, ROSH = 100 k ) CPU is in operation at high-speed oscillation (Ceramic oscillation, 2 MHz)
--
550
700
Supply Current 5
IDD5
--
850
1000
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
DC Characteristics (3)
(VDD = VDDI = VDDH = 3.0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V, VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = -20 to +70C unless otherwise specified) Parameter Output Current 1 (P9.0 to P9.3)* (PA.0 to PA.3)* (PB.0 to PB.3) (PE.0 to PE.3) Symbol Condition VDDI = 1.5 V IOH1 VOH1 = VDDI - 0.5 V VDDI = 3.0 V VDDI = 5.0 V VDDI = 1.5 V IOL1 VOL1 = 0.5 V VDDI = 3.0 V VDDI = 5.0 V Output Current 2 (MD, MDB) VDD = 1.5 V IOH2 VOH2 = VDD - 0.7 V VDD = 3.0 V VDD = VDDH = 5.0 V VDD = 1.5 V IOL2 Output Current 3 (SEG0 to SEG63) (COM1 to COM16) IOH3 IOHM3 IOHM3S IOMH3 IOMH3S IOML3 IOML3S IOLM3 IOLM3S IOL3 Output Current 4 (OSC1) IOH4R IOL4R IOH4C IOL4C Output Leakage Current (P9.0 to P9.3)* (PA.0 to PA.3)* (PB.0 to PB.3) (PE.0 to PE.3) VOL2 = 0.7 V VDD = 3.0 V VDD = VDDH = 5.0 V VOH3 = VDD5 - 0.2 V (VDD5 Ievel) VOHM3 = VDD4 + 0.2 V (VDD4 Ievel) VOHM3S = VDD4 - 0.2 V (VDD4 Ievel) VOMH3 = VDD3 + 0.2 V (VDD3 Ievel) VOMH3S = VDD3 - 0.2 V (VDD3 Ievel) VOML3 = VDD2 + 0.2 V (VDD2 Ievel) VOML3S = VDD2 - 0.2 V (VDD2 Ievel) VOLM3 = VDD1 + 0.2 V (VDD1 Ievel) VOLM3S = VDD1 - 0.2 V (VDD1 Ievel) VOL3 = VSS + 0.2 V (VSS Ievel) VOH4R = VDDH - 0.5 V (RC oscillation) VOL4R = 0.5 V (RC oscillation) VOH4C = VDDH - 0.5 V (ceramic oscillation) VOL4C = 0.5 V (ceramic oscillation) VOH = VDDI VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V Min. -2.5 -6.0 -8.5 0.4 1.0 1.5 -4.0 -11.0 -14.0 0.5 2.0 4.0 -- 4 -- 4 -- 4 -- 4 -- 4 -2.5 -3.5 0.25 0.5 -500 -800 200 400 -- Typ. -1.4 -3.5 -5.0 1.4 3.0 3.7 -2.0 -6.0 -9.0 2.0 5.5 7.0 -- -- -- -- -- -- -- -- -- -- -1.3 -1.7 1.5 1.8 -250 -350 500 700 -- Max. -0.4 -1.0 -1.5 2.5 6.0 8.5 -0.5 -2.0 -4.0 4.0 11.0 14.0 -4 -- -4 -- -4 -- -4 -- -4 -- -0.25 -0.5 2.5 3.5 -100 -200 800 1000 0.3 Unit mA mA mA mA mA mA mA mA mA mA mA mA A A A A A A A A A A mA mA mA mA A A A A A 2 Measuring Circuit
IOOH
IOOL
VOL = VSS
-0.3
--
--
A
*: Applied to the ML63189B only.
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
DC Characteristics (4)
(VDD = VDDI = VDDH = 3.0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V, VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = -20 to +70C unless otherwise specified) Parameter Input Current 1 (P0.0 to P0.3)* (P9.0 to P9.3)* (PA.0 to PA.3)* (PB.0 to PB.3) (PE.0 to PE.3) Symbol Condition VDDI = 1.5 V VDDI = 3.0 V VDDI = 5.0 V VDDI = 1.5 V IIL1 VIL1 = VSS (when pulled up) VDDI = 3.0 V VDDI = 5.0 V IIH1Z IIL1Z Input Current 2 (OSC0) IIL2 IIH2R IIL2R IIH2C IIL2C Input Current 3 (RESET) VIH1 = VDDI (in a high impedance state) VIL1 = VSS (in a high impedance state) VIL2 = VSS (when pulled up) VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V Min. 2 30 70 -45 -260 -650 0 -1 -350 -750 0 -1 0.5 3 -4.0 -10 10 150 0.5 -1 VDD = 1.5 V IIH4 IIL4 VIH4 = VDD VIL4 = VSS VDD = 3.0 V VDD = VDDH = 5.0 V 50 0.5 2.0 -1 Typ. 20 120 350 -20 -120 -350 -- -- -170 -450 -- -- 1.8 6 -1.8 -6 180 1100 2.7 -- 750 3.0 6.5 -- Max. 45 260 650 -2 -30 -70 1 0 -30 -200 1 0 4.0 10 -0.5 -3 350 2400 5.0 0 1500 5.5 11.0 0 Unit A A A A A A A A A A A A A A A A A A mA A A mA mA A 3 Measuring Circuit
IIH1
VOH1 = VDDI (when pulled up)
VIH2R = VDDH (RC oscillation) VIL2R = VSS (RC oscillation) VIH2C = VDDH (ceramic oscillation) VIL2C = VSS (ceramic oscillation) VIH3 = VDD VIL3 = VSS VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = 1.5 V VDD = 3.0 V VDD = VDDH = 5.0 V
IIH3 IIL3
Input Current 4 (TST1, TST2)
*: Applied to the ML63189B only.
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
DC Characteristics (5)
(VDD = VDDI = VDDH = 3.0 V, VDD1 = 1.1 V, VDD2 = 2.2 V, VDD3 = 3.3 V, VDD4 = 4.4 V, VDD5 = 5.5 V, Ta = -20 to +70C unless otherwise specified) Parameter Input Voltage 1 (P0.0 to P0.3)* (P9.0 to P9.3)* (PA.0 to PA.3)* (PB.0 to PB.3) (PE.0 to PE.3) Input Voltage 2 (OSC0) Symbol Condition VDDI = 1.5 V VIH1 VDDI = 3.0 V VDDI = 5.0 V VDDI = 1.5 V VIL1 VDDI = 3.0 V VDDI = 5.0 V VIH2 VIL2 Input Voltage 3 (RESET, TST1, TST2) VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = VDDH = 3.0 V VDD = VDDH = 5.0 V VDD = 1.5 V VIH3 VDD = 3.0 V VDD = 5.0 V VDD = 1.5 V VIL3 Hysteresis Width 1 (P0.0 to P0.3)* (P9.0 to P9.3)* (PA.0 to PA.3)* (PB.0 to PB.3) (PE.0 to PE.3) Hysteresis Width 2 (RESET, TST1, TST2) VDD = 3.0 V VDD = 5.0 V VDDI = 1.5 V VT1 VDDI = 3.0 V VDDI = 5.0 V VDDI = 1.5 V VT2 VDDI = 3.0 V VDDI = 5.0 V Input Pin Capacitance (P0.0 to P0.3)* (P9.0 to P9.3)* (PA.0 to PA.3)* (PB.0 to PB.3) (PE.0 to PE.3) Min. 1.2 2.4 4.0 0 0 0 2.4 4.0 0 0 1.35 2.4 4.0 0 0 0 0.05 0.2 0.25 0.05 0.2 0.25 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.1 0.5 1.0 0.1 0.5 1.0 Max. 1.5 3.0 5.0 0.3 0.6 1.0 3.0 5.0 0.6 1.0 1.5 3.0 5.0 0.15 0.6 1.0 0.3 1.0 1.5 0.3 1.0 1.5 Unit V V V V V V V V V V V V V V V V V V V V V V 4 Measuring Circuit
CIN
--
--
--
5
pF
1
*: Applied to the ML63189B only.
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
Measuring circuit 1 CB1 Cb12 CB2 C1 C12 1 2 C2 OSC0 OSC1 VSS VDD A VDDI VDD1 Ca V Ca,Cb,Cc,Cd,Ce,Cl,C12 Ch,Cb12 CG CL0 CL1 Ceramic Resonator VDD2 Cb V : : : : : : VDD3 Cc V VDD4 Cd V VDD5 Ce V VDDH Ch V VDDL Cl V
XT0 XT1
3 *2 4
*1
0.1 F 1 F 15 pF 30 pF 30 pF CSA2.00MG (2 MHz) CSB1000J (1 MHz) (Murata MFG-.make) *2 RC Oscillator
*1 RC Oscillator 1 ROSH 2 Ceramic Oscillator CL0
3 ROSL 4 Crystal Oscillator CG 3 Crystal 4
1 Ceramic Resonator 2
CL1
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
Measuring circuit 2
*3 VIH
*2 INPUT OUTPUT
A
VlL
VSS VDD VDDl VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
*2 Input logic circuit to determine the specified measuring conditions. *3 Measured at the specified output pins.
Measuring circuit 3
VIH Waveform Monitoring *4 INPUT OUTPUT
VIL
VSS
VDD
VDDl VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
*4 Measured at the specified input pins.
Measuring circuit 4
*4
A
INPUT
OUTPUT
VSS VDD VDDl VDD1 VDD2 VDD3 VDD4 VDD5 VDDH VDDL
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
AC Characteristics (Serial Interface, Shift Register)
(VDD = 0.9 to 5.5 V, VDDH = 1.8 to 5.5 V, VSS = 0 V, VDDI = 5.0 V, Ta = -20 to +70C unless otherwise specified) Parameter SCLK Input Fall Time SCLK Input Rise Time SCLK Input "L" Level Pulse Width SCLK Input "H" Level Pulse Width SCLK Input Cycle Time SCLK Output Cycle Time tCYC2(O) SOUT Output Delay Time SIN Input Setup Time SIN Input Hold Time tDDR tDS tDH Symbol tf tr tCWL tCWH tCYC tCYC1(O) Condition -- -- -- -- VDDI = 5 V to VDD CPU in operation state at 32.768 kHz CPU in operation at 2 MHz VDD = VDDH = 1.8 to 3.5 V Output load capacitance 10 pF -- -- Min. -- -- 0.8 0.8 1.8 -- -- -- 0.5 0.8 Typ. -- -- -- -- -- 30.5 0.5 -- -- -- Max. 1.0 1.0 -- -- -- -- -- 0.4 -- -- Unit s s s s s s s s s s
AC characteristics timing ("H" level = 4.0 V, "L" level = 1.0 V)
tCYC SCLK (PE.2) tr tCWH tDDR SOUT (PE.1) tDS SIN (PE.0) tDH tDS tDDR 5 V (VDDI) 0 V (VSS) tf tCWL 5 V (VDDl) 0 V (VSS)
5 V (VDDI) 0 V (VSS)
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
APPLICATION CIRCUITS (ML63187B)
* Crystal oscillation is selected as low-speed oscillation by mask option. * RC oscillation is selected as high-speed oscillation by software. * Ports are powered from external memory power source. * CV is an IC power supply bypass capacitor. * Values of Ca, Cb, Cc, Cd, Ce, Cl, Cb12, C12, Ch, and CG, are for reference only. OSC0 ROSH 5 to 25 pF 1.5 V Ch 1.0 F XT1 VDDH VDD Cv 1.0 F CB1 1.0 F Cb12 0.1 F CB2 Cl VDDL 0.1 F Ce VDD5 0.1 F Cd VDD4 0.1 F Cc VDD3 0.1 F Cb VDD2 0.1 F Ca VDD1 C1 C12 0.1 F Push SW C2 RESET TST1 TST2 MD MDB VSS OSC1 PE.3 PE.2 PE.1 PE.0 PB.3 PB.2 PB.1 PB.0
LCD
Crystal 32.768 kHz CG
COM1-16 XT0
SEG0-63
ML63187B
Buzzer
VDDl
VDD
Note:
VDDI is the power supply pin for the input-output ports. Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this device or to the positive power supply pin of the external memory. Application Circuit Example with Power Supply Backup
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
LCD
* Crystal oscillation is selected as low-speed oscillation by mask option. * Ceramic oscillation is selected as high-speed oscillation by software. * Ports, external memory, and IC share their power supply. * Cv is an IC power supply bypass capacitor. * Values of Ca, Cb, Cc, Cd, Ce, Cl, C12, CG, CL0, and CL1 are for reference only. CL0 30 pF OSC0 OSC1 PE.3 PE.2 PE.1 PE.0 PB.3 PB.2 PB.1 PB.0 CL1 30 pF Ceramic Resonator (Example: 1 MHz)
Crystal 32.768 kHz CG VDD 5.0 V 0.1 F Cv Cl Ce Cd Cc Cv Ca Open 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F Push SW
COM1-16 XT0 XT1 VDDH VDD CB1 CB2 VDDL VDD5 VDD4 VDD3 VDD2 VDD1 C1
SEG0-63
5 to 25 pF
ML63187B
C12
C2 RESET TST1 TST2 MD MDB VSS
VDDl
VDD
Buzzer
Note:
VDDI is the power supply pin for the input-output ports. Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this device or to the positive power supply pin of the external memory. Application Circuit Example with No Power Supply Backup
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
APPLICATION CIRCUITS (ML63189B)
* Crystal oscillation is selected as low-speed oscillation by mask option. * RC oscillation is selected as high-speed oscillation by software. * Ports are powered from external memory power source. * Cv is an IC power supply bypass capacitor. * Values of Ca, Cb, Cc, Cd, Ce, Cl, Cb12, C12, Ch, and CG, are for reference only. OSC0 ROSH 5 to 25 pF Ch 1.5 V 1.0 F XT1 VDDH VDD Cv 1.0 F CB1 Cb12 1.0 F CB2 Cl 0.1 F VDDL 0.1 F Ce VDD5 Cd 0.1 F VDD4 0.1 F Cc VDD3 0.1 F Cb VDD2 0.1 F Ca VDD1 C1 C12 0.1 F Push SW C2 RESET TST1 TST2 MD MDB VSS OSC1 PE.3 PE.2 PE.1 PE.0 PB.3 PB.2 PB.1 PB.0 PA.3 PA.2 PA.1 PA.0 P9.3 P9.2 P9.1 P9.0 P0.3 P0.2 P0.1 P0.0 VDDI VDD
LCD
Crystal 32.768 kHz CG
COM1-16 XT0
SEG0-63
ML63189B
Buzzer
Note:
VDDI is the power supply pin for the input and input-output ports. Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this device or to the positive power supply pin of the external memory. Application Circuit Example with Power Supply Backup
33/36
FEDL63187B-06
Semiconductor 1
ML63187B/63189B
LCD
* Crystal oscillation is selected as low-speed oscillation by mask option. * Ceramic oscillation is selected as high-speed oscillation by software. * Ports, external memory, and IC share their power supply. * Cv is an IC power supply bypass capacitor. * Values of Ca, Cb, Cc, Cd, Ce, Cl, C12, CG, CL0, and CL1 are for reference only. CL0 30 pF OSC0 OSC1 PE.3 PE.2 PE.1 PE.0 PB.3 PB.2 PB.1 PB.0 PA.3 PA.2 PA.1 PA.0 P9.3 P9.2 P9.1 P9.0 P0.3 P0.2 P0.1 P0.0 VDDl VDD CL1 30 pF Ceramic Resonator (Example: 1 MHz)
Crystal 32.768 kHz CG VDD 5.0 V
COM1-16 XT0 XT1 VDDH VDD
SEG0-63
5 to 25 pF
Cv 0.1 F Open Cl 0.1 F Ce Cd Cc Cb Ca 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F 0.1 F Push SW
CB1 CB2 VDDL VDD5 VDD4 VDD3 VDD2 VDD1 C1
ML63189B
C12
C2 RESET TST1 TST2 MD MDB VSS
Buzzer
Note:
VDDI is the power supply pin for the input and input-output ports. Be sure to connect the VDDI pin either to the positive power supply pin (VDD) of this device or to the positive power supply pin of the external memory. Application Circuit Example with No Power Supply Backup
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
PACKAGE DIMENSIONS
(Unit: mm)
QFP128-P-1420-0.50-K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 1.19 TYP. 4/Nov. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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FEDL63187B-06
Semiconductor 1
ML63187B/63189B
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd.
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